The present invention relates generally to computer processors, and more specifically, to software instructed dynamic branch history pattern adjustment.
In computer architecture, a branch predictor is a digital circuit that tries to guess which way a branch will go before this is known for sure. The purpose of the branch predictor is to improve the flow in the instruction pipeline. Branch predictors play a beneficial role in achieving high effective performance in many modern pipelined microprocessor architectures. Two-way branching is usually implemented with a conditional jump instruction. A conditional jump can either be “not taken” and continue execution with the first branch of code which follows immediately after the conditional jump, or it can be “taken” and jump to a different place in program memory where the second branch of code is stored. It is not known for certain whether a conditional jump will be taken or not taken until the condition has been calculated and the conditional jump has passed the execution stage in the instruction pipeline. Besides predicting the direction of a conditional jump, a branch predictor may also predict where the target address of a jump or a subroutine call is in program memory.
Instruction pipelining is a technique that implements a form of parallelism called instruction-level parallelism within a single processor. It therefore allows faster central processing unit (CPU) throughput (i.e., the number of instructions that can be executed in a unit of time) than would otherwise be possible at a given clock rate. The basic instruction cycle is broken up into a series called a pipeline. Rather than processing each instruction sequentially (finishing one instruction before starting the next), each instruction is split up into a sequence of steps so different steps can be executed in parallel and instructions can be processed concurrently (starting one instruction before finishing the previous one). The classic reduced instruction set computing (RISC) pipeline comprises: 1) Instruction fetch; 2) Instruction decode and register fetch; 3) Execute; 4) Memory access; and 5) Register write back.